The present invention relates to binary counters in general and in particular to a binary synchronous bit-sliced counter comprising a plurality of identical cascaded stages.
Conventional binary counters comprise a plurality of stages of flip-flops, or the like. The number of stages in a given counter depends on the capacity required.
In its implementation, the conventional binary counter requires control logic which is coupled to the flip-flops in each stage. As the capacity of a counter is increased, there is a corresponding increase in the complexity of the control logic required to implement the counter. As the complexity of the control logic increases, the amount of space required therefor on a printed circuit board, silicon chip, or the like, also increases. For relatively large capacity counters, the resulting complexity of the implementing control logic can make the task of laying out the necessary circuitry within a relatively small space, as in a VLSI circuit, very difficult, if not impossible.